1. Field of the Invention
The present invention relates to stacked type semiconductor devices and manufacturing method therefor. More specifically, the present invention relates to a stacked type semiconductor device in which semiconductor elements are formed in two or more semiconductor layers stacked with interlayer insulating films interposed therebetween, and to the manufacturing method therefor.
2. Description of the Background Art
FIG. 9 is a partial cross sectional view showing a main portion of a conventional stacked type semiconductor device. The structure of the conventional stacked type semiconductor device will be described in the following with reference to FIG. 9.
An isolating oxide film 2 formed of silicon oxide is formed surrounding an element forming region on a main surface of a single crystal silicon substrate (hereinafter referred to as a substrate) 1 of a first conductivity type, for example, p type. A first layer MOS transistor is formed in the element forming region. The first layer MOS transistor comprises a gate electrode 3 and impurity diffused regions 5 and 6 of a second conductivity type, for example, n type, serving as a pair of source.drain regions formed on the main surface of the substrate 1 on both sides of the gate electrode 3. The gate electrode 3 is formed of polycrystalline silicon doped to a high concentration with phosphorous, on a substrate 1 with a gate insulating film 4 interposed therebetween. An insulating layer 7 of silicon oxide film is formed covering the gate electrode 3. First interconnection layers 8 and 9 formed of refractory metal silicide such as tungsten silicide, molybdenum silicide or the like are connected to the impurity diffused regions 5 and 6 serving as source/drain regions, respectively.
An interlayer insulating film 10 is formed over the first layer MOS transistor. The interlayer insulating film 10 is of a silicon oxide film formed by low pressure CVD method (chemical vapor deposition) on the first interconnection layers 8 and 9 and on the insulating layer 7. The interlayer insulating film is about 1.5 to 2.mu.m in thickness. On the interlayer insulating film 10, there is a semiconductor layer 11 having a first conductivity type formed of a single crystal silicon which is an island surrounded by isolating regions 12 of silicon oxide films. The upper semiconductor layer 11 is formed to have an approximately rectangular projected planar shape. A second layer MOS transistor is formed in the upper semiconductor layer 11. The second layer MOS transistor comprises a gate electrode 13 and impurity diffused regions 15 and 16 of the second conductivity type serving as a pair of source.drain regions formed on the main surface of the upper semiconductor layer 11 on both sides of the gate electrode. The gate electrode 13 is formed of polycrystalline silicon doped to a high concentration with phosphorous on the surface of the upper semiconductor layer 11 with a gate insulating film 14 interposed therebetween. An insulating layer 17 formed of silicon oxide film covers the gate electrode 13. Second interconnection layers 18 and 19 are respectively connected to the impurity diffused regions 15 and 16 serving as a pair of source.drain regions. The second interconnection layers 18 and 19 are formed of, for example, aluminum.
In the stacked type semiconductor device structured as described above, the first layer MOS transistor and the first interconnection layers 8 and 9 are separated from the second layer MOS transistor by the interlayer insulating film 10 formed of a silicon oxide film having the thickness of 1.5 to 2.0.mu.m. Instead of the silicon oxide film, a silicon oxide film doped with boron and phosphorus (hereinafter referred to as a BPSG film: boro-phospho silicate glass film) or a silicon oxide film doped with phosphorous (hereinafter referred to as PSG film: phospho silicate glass film) may be used as the interlayer insulating film.
Examples of the conventional stacked type semiconductor devices employing the BPSG film or the PSG film as the interlayer insulating film are disclosed in preceedings of Spring Conference of the Japan Society of Applied Physics 1984, "Experimental Manufacture of Three Dimensional CMOSIC Having SOI Double Layer Structure by Laser Irradiation" and in Japanese Patent Laying Open No. 58-7861. In the former article disclosed is an interlayer insulating film having double layer structure of Si.sub.3 N.sub.4 film and PSG film. In the latter article, disclosed is an interlayer insulating film having a three layer structure of a silicon oxide film, the PSG film and a silicon oxide film or a silicon nitride film. The silicon oxide film or the silicon nitride film has a low impurity concentration.
In the stacked type semiconductor device shown in FIG. 9, the island-like semiconductor layer 11 serving as a substrate for the second layer MOS transistor is formed by melting and recrystalizing polycrystalline silicon layer formed on the interlayer insulating film 10 by irradiation of energy line such as laser beam on the polycrystalline silicon layer. Namely, the semiconductor layer 11 is once heated to 1420.degree. C., which is the melting point of silicon, and thereafter it is cooled to the room temperature. Meanwhile, the glass transition point of the silicon oxide formed by the CVD method serving as the interlayer insulating film 10 is 1150.degree. C. Therefore, when the semiconductor layer 11 is melted, the interlayer insulating film 10 in contact with the semiconductor layer 11 becomes viscous. The glass transition point means a temperature at which the coefficient of viscosity of a material is 10.sup.12 poise (g/cm.sup.2 .multidot.sec).
The coefficient of thermal expansion of silicon is 5.times.10.sup.-6 /.degree.C., while the coefficient of thermal expansion of the silicon oxide is 5.times.10.sup.-7 /.degree.C. The difference of the coefficient between the two is of the order of one rank. Due to the difference of the coefficient of thermal expansion, a tensile stress of about 10.sup.9 dyne/cm.sup.2 remains in the semiconductor layer 11 in the course of melting, recrystalization and cooling to the room temperature of the semiconductor layer 11. The remaining tensile stress causes distortion of the semiconductor layer 11. Consequently, the characteristics of the device such as current handling capability of the second layer MOS transistor formed in the distorted semiconductor layer 11 are degraded. The reason for this may be reduction of mobility of electrons caused by the existence of the remaining tensile stress in the material.
How the tensile stress remains in the semiconductor layer 11 will be described in the following. A polycrystalline silicon layer is formed on the silicon oxide film serving as the interlayer insulating film 10. By the irradiation of energy line such as laser beam on the polycrystalline silicon layer, the polycrystalline silicon layer is melted and recrystalized. On this occasion, the polycrystalline silicon layer is heated to 1420.degree. C. which is the melting point of silicon. Thereafter, the semiconductor layer 11 formed of single crystal silicon formed by recrystalization is cooled to room temperature. In the course of cooling, the interlayer insulating film 10 below the semiconductor layer 11 is also kept in the melt state until it is cooled to 1150.degree. C. which is the glass transition point of silicon oxide. Therefore, the semiconductor layer 11 contracts without restriction by the interlayer insulating film 10. However, when it is cooled further from 1150.degree. C. to the room temperatrure, the interlayer insulating film 10 is in the solid state, so that the semiconductor layer 11 contracts restricted by the interlayer insulating film 10. More specifically, the semiconductor layer 11 is cooled to the room temperature strained by the interlayer insulating film 10. Thus, tensile stress remains in the semiconductor layer 11.
In the foregoing, description was given of two layers of MOS transistors. When three or more MOS transistors are formed, the interlayer insulating film directly below the semiconductor layer of the uppermost MOS transistor becomes thick. For example, the thickness of the interlayer insulating film directly below the MOS transistor of the third layer may be double of the MOS transistor in the second layer. Therefore, the above described problem of distortion in the upper semiconductor layer becomes more serious. When the stress is larger than 10.sup.10 dyne/cm.sup.2 which is the yield stress of silicon, there may possibly be a crack in the upper semiconductor layer.
When a BPSG film is used as the interlayer insulating film 10 instead of the silicon oxide film, the distortion generated in the upper semiconductor layer 11 can be reduced to 1/3 to 2/3 compared with the case of the silicon oxide film. The reason for this may be the fact that the glass transition point of the BPSG film is 650.degree. C. which is lower than that of the silicon oxide film. More specifically, when the silicon oxide is used as the interlayer insulating film 10, it becomes solid at 1150.degree. C. during cooling of the upper semiconductor layer. Meanwhile, when the BPSG film is used as the interlayer insulating film, it becomes solid at a lower temperature, that is, 650.degree. C., which contributes to the reduction of distortion in the upper semiconductor layer 11.
However, in this type of stacked type semiconductor devices, the width of the semiconductor regions melted by irradiation of energy line is as narrow as 0.1 to 1 mm. The width of this region to be melted is very small compared with the size of the semiconductor substrate (4 inch substrate has a diameter of 100 mm, 6 inch substrate has a diameter of 150 mm). Therefore, distortion is generated between the semiconductor layer which is melted and the semiconductor layer which is not melt, due to the difference of temperature. Consequently, lateral planar distortion remains in the semiconductor layer 11. The distortion of the melt semiconductor layer is reduced by the BPSG film below the semiconductor layer, which BPSG film has its coefficient of viscosity lowered. However, the coefficient of viscosity of the BPSG film below the semiconductor layer which is not melted is not sufficiently reduced to eliminate the distortion at the boundary between the portions which are melted and the portions which are not melted. Therefore, even if the BPSG film is used as the interlayer insulating film 10, the characteristics of the second layer MOS transistor is degraded.
What is disclosed in the above mentioned article and the gazette is an interlayer insulating film having two layers of different materials. There is no consideration of the relation between the semiconductor layer and interlayer insulating film in association with the distortion or crack generated in the semiconductor layer in the course of melting and recrystalizing the upper semiconductor layer formed on the interlayer insulating film.